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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_PFR2_EL1, AArch32 Processor Feature Register 2</h1><p>The ID_PFR2_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Gives information about the AArch32 programmers' model.</p>

      
        <p>Must be interpreted with <a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1</a> and <a href="AArch64-id_pfr1_el1.html">ID_PFR1_EL1</a>.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch64 System register ID_PFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-id_pfr2.html">ID_PFR2[31:0]</a>.</p>
        <div class="note"><span class="note-header">Note</span><p>Prior to the introduction of the features described by this register, this register was unnamed and reserved, <span class="arm-defined-word">RES0</span> from EL1, EL2, and EL3.</p></div>
      <h2>Attributes</h2>
        <p>ID_PFR2_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When AArch32 is supported:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_12">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="20"><a href="#fieldset_0-63_12">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">RAS_frac</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">SSBS</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">CSV3</a></td></tr></tbody></table><h4 id="fieldset_0-63_12">Bits [63:12]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-11_8">RAS_frac, bits [11:8]</h4><div class="field">
      <p>RAS Extension fractional field. Defined values are:</p>
    <table class="valuetable"><tr><th>RAS_frac</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>If <a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1</a>.RAS == <span class="binarynumber">0b0001</span>, RAS Extension implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>If <a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1</a>.RAS == <span class="binarynumber">0b0001</span>, as <span class="binarynumber">0b0000</span> and adds support for additional ERXMISC&lt;m&gt; System registers.</p>
<p>Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> and support for the optional RAS Timestamp Extension.</p></td></tr></table><p>All other values are reserved.</p>
<p>This field is valid only if <a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1</a>.RAS == <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-7_4">SSBS, bits [7:4]</h4><div class="field">
      <p>Speculative Store Bypassing controls in AArch64 state. Defined values are:</p>
    <table class="valuetable"><tr><th>SSBS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>AArch32 provides no mechanism to control the use of Speculative Store Bypassing.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe.</p>
        </td></tr></table><p>In Armv8.0, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.5, the only permitted value is <span class="binarynumber">0b0001</span>.</p>
<p>All other values are reserved.</p></div><h4 id="fieldset_0-3_0">CSV3, bits [3:0]</h4><div class="field">
      <p>Speculative use of faulting data. Defined values are:</p>
    <table class="valuetable"><tr><th>CSV3</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>This PE does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by other instructions in the speculative sequence.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Data loaded under speculation with a permission or domain fault cannot be used to form an address, generate condition codes, or generate SVE predicate values to be used by other instructions in the speculative sequence. The execution timing of any other instructions in the speculative sequence is not a function of the data loaded under speculation.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_CSV3</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>In Armv8.0, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.5, the only permitted value is <span class="binarynumber">0b0001</span>.</p>
<p>If <span class="xref">FEAT_E0PD</span> is implemented, <span class="xref">FEAT_CSV3</span> must be implemented.</p></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">UNKNOWN</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">UNKNOWN</a></td></tr></tbody></table><h4 id="fieldset_1-63_0">Bits [63:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing ID_PFR2_EL1</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, ID_PFR2_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0000</td><td>0b0011</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_PFR2_EL1) || boolean IMPLEMENTATION_DEFINED "ID_PFR2_EL1 trapped by HCR_EL2.TID3") &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        X[t, 64] = ID_PFR2_EL1;
elsif PSTATE.EL == EL2 then
    X[t, 64] = ID_PFR2_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = ID_PFR2_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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